Cache hierarchy
Cache hierarchy is the tiered L1/L2/L3 memory between cores and RAM, trading capacity for latency so most accesses never reach main memory.
Also known as L1 cache, L2 cache, L3 cache, CPU cache
Not measurable from a browser
A browser cannot read temperatures, power draw, fan speed, VRAM capacity, clock frequency or native FLOPS. For a direct reading use a native monitor such as HWiNFO64, GPU-Z or lm-sensors. SystemCheck contributes the other half: whether the condition is costing you throughput, measured as decay and consistency.
L1 is a few tens of kilobytes per core at roughly 4-5 cycles of latency. L2 is hundreds of kilobytes to a couple of megabytes at 12-20 cycles. L3 is tens to hundreds of megabytes shared across cores at 40-70 cycles. Main memory is 200-400 cycles away. Each level exists because the one below it is an order of magnitude slower.
Whether your working set fits a level determines performance far more than clock speed does. This is why AMD's large-L3 X3D parts win decisively in games (game simulation data fits in the bigger cache) while showing no advantage in rendering, whose working set never fits any cache.
Cache effects are also the main reason a benchmark's result depends on its data size. SystemCheck's CPU workload uses a fixed working set, so results stay comparable across runs and machines, but it means a SystemCheck score is not a proxy for how a cache-sensitive game will behave on the same chip. Read them as different questions.
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