PCIe lanes
PCIe lanes are the high-speed serial links connecting the CPU to the GPU, NVMe drives, and other devices, and they are a finite budget on every platform.
Also known as PCI Express lanes, lane allocation
Not measurable from a browser
A browser cannot read temperatures, power draw, fan speed, VRAM capacity, clock frequency or native FLOPS. For a direct reading use a native monitor such as HWiNFO64, GPU-Z or lm-sensors. SystemCheck contributes the other half: whether the condition is costing you throughput, measured as decay and consistency.
A consumer CPU provides a limited number of lanes, commonly 20-28, split between the graphics slot and one or two NVMe slots, with the chipset providing more lanes behind a shared uplink. Populating certain M.2 slots can drop the graphics slot from x16 to x8, and that is documented only in the motherboard manual's fine print.
Each generation doubles per-lane bandwidth, so a PCIe 5.0 x8 link carries as much as PCIe 4.0 x16. For most GPUs the difference between x16 and x8 at a current generation is 1-3%, but it grows sharply for cards with narrow lane widths or limited VRAM, where PCIe traffic substitutes for missing local memory.
A browser has no visibility into link width or generation. Read them in GPU-Z's bus interface field, which also has a render test to show the active link state. If SystemCheck's GPU results are far below expectation for your card, a downgraded link is one thing worth ruling out early because it is cheap to check.
Related terms